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? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 half-bridge gate-drive ic september 2006 FAN7383 rev. 1.0.0 FAN7383 half-bridge gate-drive ic features ? floating channel designed for bootstrap operation to +600v. ? typically 350ma/650ma sourcing/sinking current driving capability for both channels ? extended allowable negative v s swing to -9.8v for signal propagation at v dd =v bs =15v ? high-side output in phase of in input signal ? built-in uvlo functions for both channels ? built-in common-mode dv/dt noise canceling circuit ? typically internal 330nsec minimum dead time ? programmable turn-on delay time control (dead time) applications ? smps ? motor drive inverter ? fluorescent lamp ballast ? hid ballast description the FAN7383 is a half-bridge gate-drive ic with shutdown and programmable dead-time control functions for driving mosfet s and igbts that operate up to +600v. fairchild?s high voltage process and common-mode noise canceling technique give stable operation of high- side drivers under high-dv/dt noise circumstances. an advanced level-shift circuit allows high-side gate driver operation up to v s = -9.8v (typical) for v bs =15v. the uvlo circuits for both channels prevent malfunction when v dd and v bs are lower than the specified threshold voltage. output drivers typically source/sink 350ma/650ma, respectively, which is suitable for all kinds of half and full bridge inverter. ordering information 1 14-sop part number package pb-free operating temperature range packing method FAN7383m 14-sop yes -40c ~ 125c tube FAN7383mx tape & reel
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 2 typical application circuit figure 1. application circuit for half-bridge switch ing power supply figure 2. application circuit for full-bridge dc motor driver v dd v dc pwm shutdown lo1 gnd v b v s ho1 v dd sd in dt nc 9 10 8 11 14 12 13 6 5 7 4 1 3 2 lo2 nc nc ho2 pwm ic control r dt d boot c boot r hon r hoff r lon r loff FAN7383 rev:00 forward ho1 v s lo2 v b v dd gnd in FAN7383 v dc v cc m reverse dt dc motor controller pha phb lo1 ho2 sd ho1 v s lo2 v b v dd gnd in FAN7383 dt lo1 ho2 sd sd FAN7383 rev:00
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 3 internal block diagram figure 3. functional block diagram of FAN7383 uvlo driver pulse generator 2 4 7 14 11 in v dd gnd lo1 v b ho1 v s r r s q driver hs(on/off) ls(on/off) delay dt uvlo 1 3 ho2 lo2 schmitt trigger input shoot though prevention dead-time { dtmin=330nsec } noise canceller sd 5 13 12 6 FAN7383 rev:01
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 4 pin configuration figure 4. pin configuration (top view) pin definitions pin # name description 1 in logic input for gate driver 2sd logic input for shutdown (active low) 3 dt programmable dead-time control with external resistor 4v dd low side supply voltage 5 lo1 low side driver source output 6 lo2 low side driver sink output 7 gnd ground 8 nc not connected 9 nc not connected 10 nc not connected 11 v s high side floating supply return 12 ho2 high side driver sink output 13 ho1 high side driver source output 14 v b high side floating supply lo2 lo1 gnd nc v s FAN7383 in v dd ho2 ho1 v b dt nc nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sd FAN7383 rev:00
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 5 absolute maximum ratings the ?absolute maximum ratings? are those values beyond wh ich the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. th e ?recommended operating conditions? table defines the conditions for actual device operation. t a = 25c unless otherwise specified. notes: 1. when mounted on 76.2 x 114.3 x 1.6mm pcb. (fr-4 glass epoxy material). 2. please refer to: jesd51-2: integral circuits thermal test method environmental conditions - natural convection jesd51-3: low effective thermal conductiv ity test board for leaded surface mount packages 3. do not exceed p d under any circumstances. recommended oper ating conditions symbol parameter min. max. unit v s high-side offset voltage v b -25 v b +0.3 v v b high-side floating supply voltage -0.3 625 v v ho high-side floating output voltage ho1, ho2 v s -0.3 v b +0.3 v v dd low-side and logic fixed supply voltage -0.3 25 v v lo low-side output voltage lo1, lo2 -0.3 v dd +0.3 v v in logic input voltage (in) -0.3 v dd +0.3 v v sd shutdown logic input voltage -0.3 v dd +0.3 v v dt dead-time control voltage -0.3 5.0 v gnd logic ground v dd -25 v dd +0.3 v dv s /dt allowable offset voltage slew rate 50 v/nsec p d (1)(2)(3) power dissipation 1.0 w ja thermal resistance, junction-to-ambient 110 c/w t j junction temperature 150 c t stg storage temperature 150 c symbol parameter condition min. max. unit v b high-side floating supply voltage v s +15 v s +20 v v s high-side floating supply offset voltage 6-v dd 600 v v dd low-side supply voltage 15 20 v v ho high-side (ho) output voltage v s v b v v lo low-side (lo) output voltage gnd v dd v v in logic input voltage (in) gnd v dd v t a ambient temperature -40 125 c
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 6 electrical characteristics v bias (v dd , v bs ) = 15.0v, r dt = gnd, t a = 25 c, unless otherwise specified. the v in and i in parameters are referenced to gnd. the v o and i o parameters are referenced to gnd and v s is applicable to ho and lo. note: 4. this parameter, although guaranteed, is not 100% tested in production. symbol characteristics test condition min. typ. max. unit supply current section i qbs quiescent v bs supply current v in =0v or 5v 35 90 a i qdd quiescent v dd supply current v in =0v or 5v, r dt =0 650 900 i sd (4) v dd supply current at shutdown mode sd =gnd 650 900 i pbs operating v bs supply current f in =20khz,rms value 400 700 i pdd operating v dd supply current f in =20khz,rms value,r dt =0 950 1200 i lk offset supply leakage current v b =v s =600v 10 power supply section v dduv+ v bsuv+ v dd and v bs supply under-voltage positive going threshold 10.7 11.6 12.5 v v dduv- v bsuv- v dd and v bs supply under-voltage negative going threshold 10.0 10.8 11.6 v dduvh v bsuvh v dd and v bs supply under-voltage lockout hysteresis 0.8 gate driver output section v oh high-level output voltage, v bias -v o i o =20ma 1.0 v v ol low-level output voltage, v o 0.6 v i o+ output high short-circuit pulse current v o =0v, v in =5v with pw<10s 250 350 ma i o- output low short-circuit pulsed current v o =15v, v in =0v with pw<10s 500 650 ma v s allowable negative v s pin voltage for in signal propagation to ho -9.8 -7.0 v logic input section (input and shutdown) v ih logic "1" input voltage 2.9 v v il logic "0" input voltage 1.2 v i in+ logic "1" input bias current v in =5v 50 100 a i in- logic "0" input bias current v in =0v 2.0 a sd+ shutdown "1" input voltage 1.2 v sd- shutdown "0" input voltage 2.9 v r pd input pull-down resistance 100 k
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 7 dynamic electrical characteristics v bias (v dd , v bs ) = 15.0v, v s = gnd, c l =1000pf, r dt = gnd, and t a = 25 c, unless otherwise specified. note: 5. this parameter, although guaranteed, is not 100% tested in production. symbol parameter conditions min. typ. max. unit t on turn-on propagation delay v s =0v 500 670 nsec t off turn-off propagation delay v s =0v 170 250 t r turn-on rise time 50 100 t f turn-off fall time 30 80 t sd (5) shutdown propagation delay 100 180 dt1, dt2 dead-time lo off to ho on and ho off to lo on r dt =0 250 330 420 r dt = 200k 1.20 1.68 2.30 dmt dead-time matching r dt =0 060 r dt =200k 0150
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 8 typical characteristics figure 5. v dd / v dd uvlo (+) vs. temperature figure 6. v dd / v bs uvlo (-) vs. temperature figure 7. v dd quiescent current vs. temperature figure 8. v bs quiescent current vs. temperature figure 9. v dd operating current vs. temperature figure 10. v bs operating current vs. temperature -40 -20 0 20 40 60 80 100 120 10.8 11.0 11.2 11.4 11.6 11.8 12.0 v dduv+ ,v bsuv+ [v] temperature [c] -40 -20 0 20 40 60 80 100 120 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6 v dduv- ,v bsuv- [v] temperature [c] -40 -20 0 20 40 60 80 100 120 200 400 600 800 1000 i qdd [ a] temperature [c] -40-20 0 20406080100120 0 20 40 60 80 100 i qbs [ a] temperature [c] -40 -20 0 20 40 60 80 100 120 400 600 800 1000 1200 1400 1600 i pdd [ a] temperature [c] -40 -20 0 20 40 60 80 100 120 0 200 400 600 800 i pbs [ a] temperature [c]
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 9 typical characteristics (continued) figure 11. logic input current vs. temperature figure 12. logic input high voltage vs. temperature figure 13. logic input low voltage vs. temperature figure 14. sd positive threshold vs. temperature figure 15. sd negative threshold vs. temperature figure 16. rising time vs. temperature -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 100 i in+ [ a] temperature [c] -40-20 0 20406080100120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ih [v] temperature [c] -40 -20 0 20 40 60 80 100 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v il [v] temperature [c] -40-20 0 20406080100120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 sd+ bar [v] temperature [c] -40-20 0 20406080100120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 sd- bar [v] temperature [c] -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 100 t r [nsec] temperature [c]
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 10 typical characteristics (continued) figure 17. falling time vs. temperature figure 18. turn-on delay time vs. temperature figure 19. turn-off falling time vs. temperature figure 20. dead-time (r dt =0k ) vs. temperature figure 21. dead-time (r dt =200k ) vs. temperature figure 22. r dt vs. dead-time -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 t f [nsec] temperature [c] -40 -20 0 20 40 60 80 100 120 200 300 400 500 600 700 t on [nsec] temperature [c] -40-20 0 20406080100120 0 50 100 150 200 250 300 t off [nsec] temperature [c] -40-20 0 20406080100120 240 280 320 360 400 d t1 , r dt = 0 [nsec] temperature [c] -40 -20 0 20 40 60 80 100 120 1.2 1.4 1.6 1.8 2.0 2.2 2.4 d t1 , r dt = 200k [nsec] temperature [c] 0 20 40 60 80 100 120 140 160 180 200 0.0 0.4 0.8 1.2 1.6 2.0 deadtime [ s] rdt [kohm]
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 11 typical characteristics (continued) figure 23. allowable negative v s voltage for signal propagation to high side vs. temperature -40 -20 0 20 40 60 80 100 120 -14 -12 -10 -8 -6 v s [v] temperature [c]
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 12 switching time definitions figure 24. switching time test circuit figure 25. input / output waveforms figure 26. switching time waveform definitions +15v sd lo1 gnd v b v s ho1 v dd sd in FAN7383 10 f 100nf 1nf 1nf +15v 100nf 10 f dt nc 9 10 8 11 14 12 13 6 5 7 4 1 3 2 lo2 nc nc ho2 ho1, 2 lo1, 2 FAN7383 rev:00 in ho1, 2 lo1, 2 sd dt1 dt2 dt1 dt2 dt1 shutdown shutdown FAN7383 rev:00 in ho1, 2 lo1, 2 10% 90% 50% 50% 90% 10% t off t off t on t on FAN7383 rev:00
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 13 figure 27. shutdown waveform definition figure 28. dead-time waveform definition 90% 50% t sd ho or lo sd FAN7383 rev:00 ho 10% 90% dt1 lo 90% 10% dt2 mdt= dt1-dt2 FAN7383 rev:00
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 14 typical application information 1. normal operating consideration the FAN7383 is a single pwm input half-bridge gate- drive ic with programmable dead-time and shutdown function. the dead-time is set with a resistor(r dt ) at the dt pin. the wide dead-time programming range provides the flexibility to optimize drive signal timing for a selection of switching devices (mosfet or igbt) and applications. the turn-on time delay circuitry (dead-time) accommodates resistor values from 0 to 200k with a dead-time proportional to the r dt resistance. grounding the dt pin programs the FAN7383 to drive both outputs with minimum dead time. if the sd pin voltage decreases below 1.2v in normal operation, the ic enters the shutdown mode. 2. under voltage lockout (uvlo) the FAN7383 has an under-voltage lockout (uvlo) protection circuitry for high and low side channels to prevent malfunction when v dd or v bs is lower than the specified threshold voltage. the uvlo circuitry monitors the supply voltage (v dd ) and bootstrap capacitor voltage (v bs ) indepently. 3. layout consideration for optimum performance of high- and low-side gate drivers, considerations must be taken during printed circuit board (pcb) layout. 3.1 supply capacitors if the output stages are able to quickly turn on the switching device with high value of current, the supply capacitors must be placed as close as possible to the device pins (v dd and gnd for the ground-tied supply, v b and v s for the floating supply) to minimize parasitic inductance and resistance. 3.2 gate drive loop current loops behave like an antenna, able to receive and transmit noise. to reduce the noise coupling/ emission and improve the power switch turn-on and off performances, gate drive loops must be reduced as much as possible. 3.3 ground plane ground plane must not be placed under or nearby the high-voltage floating side to minimize noise coupling.
FAN7383 half-bridge gate-drive ic ? 2006 fairchild semiconductor corporation www.fairchildsemi.com FAN7383 rev. 1.0.0 15 package dimensions 14-sop dimensions are in millimeter s unless otherwise noted. january 2001, rev. a 8.56 0.20 0.337 0.008 1.27 0.050 5.72 0.225 1.55 0.10 0.061 0.004 0.05 0.002 6.00 0.30 0.236 0.012 3.95 0.20 0.156 0.008 0.60 0.20 0.024 0.008 8.70 0.343 max #1 #7 #8 0~8 #14 0.47 0.019 () 1.80 0.071 max0.10 max0.004 max min + 0.10 -0.05 0.20 + 0.004 -0.002 0.008 + 0.10 -0.05 0.406 + 0.004 -0.002 0.016
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